The present invention relates to semiconductor memory devices, and more particularly, to a repair control circuit of a semiconductor memory device.
In general, a semiconductor memory device is designed to include a redundancy memory cell array in order to repair fail cells generated during a manufacturing process. Therefore, a row line or column line of a main memory cell array having one or more fail cells can be substituted by the redundancy memory cells.
FIG. 1 is a schematic block diagram of a repair control circuit, a normal decoder and a redundancy decoder of a semiconductor memory device in the related art. Referring to FIG. 1, the repair control circuit 10 includes a fuse box 11 and a control signal generator 12.
An address of a fail cell to be repaired is previously programmed into the fuse box 11. The fuse box 11 compares a received address (ADD) and its programmed address and outputs a compare signal (COM) according to the comparison result.
The control signal generator 12 outputs a control signal (CTL) for selectively enabling one of the normal decoder 20 and the redundancy decoder 30 in response to the compare signal (COM). As described above, the repair control circuit 10 employs the fuse box 11, which is a circuit that programs an address of a fail cell. In this case, as fuses (not shown) included in the fuse box 11 are selectively cut by a laser, an address of a fail cell is programmed into the fuse box 11. In order for the fuses to be easily cut by a laser, however, the fuses must be designed to have a relatively large size. An occupation area of the fuse box 11 serves as a limiting factor in increasing the level of integration of semiconductor memory devices and reducing the chip size.
Furthermore, these problems become more profound when the number of fail cells to be repaired is increased. That is, the greater the number of redundancy memory cells, the greater the number of fuses included in the fuse box 11. Therefore, a problem arises because the occupation area is increased.